PsramPhySdr

PsramPhySdr

PsramPhySdrCore の IOBUF ラッパ (Top 統合用)

Ports

i_clk	input	clock
i_rst	input	reset
o_en	output	logic	FSM 状態更新イネーブル
i_ck_en	input	logic
i_cs_n	input	logic
i_reset_n	input	logic
i_dq_a	input	logic<8>
i_dq_b	input	logic<8>
i_dq_oe	input	logic
i_rwds_a	input	logic
i_rwds_b	input	logic
i_rwds_oe	input	logic
o_dq_a	output	logic<8>
o_dq_b	output	logic<8>
o_rwds_a	output	logic
o_rwds_b	output	logic
o_pad_ck	output	logic
o_pad_ck_n	output	logic
o_pad_cs_n	output	logic
o_pad_reset_n	output	logic
io_pad_dq	inout	trilogic<8>
io_pad_rwds	inout	trilogic